Cart 2 india

Specification
Brand : Juried Engineering
BulletPoint1 : The CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit.
BulletPoint2 : Clock polarity control, Q and Q outputs, Common Clock, Noise margin (full package-temperature range) = 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
BulletPoint3 : Low power TTL compatible, Standardized, symmetrical output characteristics, 100% tested for quiescent current at 20 V
BulletPoint4 : Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C, 5-V, 10-V, and 15-V parametric ratings
BulletPoint5 : Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices", Example Applications: Buffer storage, Holding register, General digital logic
ExternallyAssignedProductIdentifier1 : 0799993465087
ExternallyAssignedProductIdentifier2 : 799993465087
ItemName : Juried Engineering CD4042BE CD4042 CD4042 CMOS Quad Clocked 'D' Latch Breadboard-Friendly IC DIP-16 (1 Piece)
ItemPackageQuantity : 1
ItemTypeKeyword : timing-integrated-circuits
Manufacturer : TI
Material : PDIP
ModelNumber : CD4042BE
NumberOfItems : 1
PartNumber : CD4042BE
ProductDescription : The CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
ProductSiteLaunchDate : 2020-07-14T21:10:49.232Z
Size : Juried Engineering ESD Safe Packaging (1 Piece)